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ADE7816
REGISTERS
REGISTER PROTECTION
To protect the integrity of the data stored in the data memory
(located at Address 0x4380 to Address 0x43BE), a write protection
mechanism is available. By default, the protection is disabled,
and registers that are located between Address 0x4380 and
Address 0x43BE can be written without restriction. When the
protection is enabled, no writes to these registers are allowed.
Registers can always be read, without restriction, independent
of the write protection state.
To enable the protection, write 0xAD to an internal 8-bit
register that is located at Address 0xE7FE, followed by a write
of 0x80 to an internal 8-bit register located at Address 0xE7E3.
It is recommended that the write protection be enabled before
Data Sheet
REGISTER FORMAT
The ADE7816 includes 8-, 16-, and 32-bit, signed and unsigned
registers. All signed registers are in twos complement format.
Some of the internal measurements are 24 bits long and have
been extended to 32 bits prior to communication. This extension
is accomplished in three different ways: sign extending (SE), zero
padding (ZP), or zero padded and sign extended (ZPSE). When
sign extending is used, the sign bit (Bit 23) of the twos complement
signed number is duplicated in the uppermost byte prior to
communication. Zero padding is achieved by writing 0s into the
upper most byte prior to transmission. This format is used for
unsigned numbers only. Zero padded and sign extended formats
are shown in Figure 47 and involve padding the most significant
bits with 0s and sign extending Bits[27:24].
starting the DSP. If any register requires changing after this time,
disable the protection, change the value, and then reenable the
31
0000
28 27
24 23
24-BIT NUMBER
0
protection. There is no need to stop the DSP to change these
registers.
BITS[27:24] ARE
BIT 23 IS A SIGN BIT
To disable the protection, write 0xAD to an internal 8-bit
register that is located at Address 0xE7FE, followed by a write of
0x00 to an internal 8-bit register that is located at Address 0xE7E3.
EQUAL TO BIT 23
Figure 47. ZPSE Communication Format
The communication format of each register is specified in the
Register Maps section (see Table 12 through Table 15).
Rev. A | Page 36 of 48
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